Year3rd-year
ProgramECE @ UofT
FocusAnalog/Digital • Hardware
MinorEngineering Business
BasedToronto, ON
Emaildianajunguoftece@gmail.com
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Hi there!
I’m Diana

Verilog
Waveform
PCB
clk valid data[7:0] leds
PCB preview
println("Reaching for the stars…");
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About

I design and deliver hardware systems that perform, from first schematic to lab-validated product, while leading teams to execute with clarity and speed.

Core Skills
PCB design (2–4 layers) from placement & routing to bring-up & validation
FPGA/RTL development in Verilog & SystemVerilog with timing closure
Embedded STM32 development with UART, I²C, SPI, and LoRa/RF links
Leadership & Approach
Led cross-functional engineering teams to deliver race-ready hardware
Defined roadmaps, risk registers, and test plans to align stakeholders
Presented technical results to senior leadership with clear, actionable data
>2 km RF link 80% TX power reduction Cross-functional coordination Technical presentations

Highlights

550+
Leaders mentored for Frosh Week
5+
Custom PCBs from schematic to scope
LoRa
Redesign Radio system @ Blue Sky Solar Racing

Experience

Blue Sky LoRa
>2 km range STM32WL USB-CDC Program Lead Cross-Functional

Radio Systems Co-Lead

Blue Sky Solar Racing • Jan 2025 – Present
  • Defined radio system architecture for LoRa telemetry redesign, coordinating hardware–firmware–test integration on a race-critical timeline.
  • Executed PCB design and bring-up of STM32WL-based RF link, achieving 2 km validated range and ~30% fewer sequencing failures via standardized debug flows.
Roadmap/Milestones Supplier Mgmt. Altium LTspice
Repository
FPGA AV System
100 MHz VGA • PS/2 • PWM Tcl/Bash CI-like Verification Research Lead

FPGA Design — Embedded AV Systems

Korea University • May 2025 – Sep 2025
  • Led research track & design reviews; aligned RTL, testbench, and synth owners; hit timing at 100 MHz with <10% LUT, <5% BRAM.
  • Automated Quartus synth & ModelSim runs with Tcl/Bash (deterministic one-command builds); structured verification with focused benches and pass/fail artifacts.
Quartus ModelSim Stakeholder Updates
Repository

Projects

LoRa Telemetry Module

STM32WL • custom CRC • USB-CDC • RF validation
LoRa Radio PCB
C / STM32 HAL LoRa / RF CRC / Packets USB-CDC Altium

Chase & car modules with live data routing to the vehicle network. Clean packet design and scope-verified performance.

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SDR Controller Hardware

ATmega324PB • Si5351A • UART CAT • I/Q
SDR Controller Render
AVR C Si5351A UART CAT I/Q Python Tools

LO generation & RX/TX switching with ±1 kHz stability and accurate 90° I/Q. Firmware + Python automation for validation.

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RISC-V 5-Stage Pipelined CPU

RV32I • hazards/forwarding • branches
RISC-V CPU Block Diagram
SystemVerilog ModelSim Quartus Coverage Tcl Regressions

Synthesizable CPU with coverage-driven verification. Tcl-driven regressions and waveform triage accelerate iteration.

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FPGA Nios® V Hearing Loss & Aid Simulator

8 ms latency • 100 MHz • 12% LUT
FPGA Hearing UI
Verilog Nios® V VGA UI PS/2 Audio DSP

Real-time DSP on DE1-SoC with VGA UI and PS/2 controls. Measured latency & behavior match design goals.

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Skills

Leadership

Guiding cross-functional teams to hit aggressive timelines with clarity, accountability, and momentum.

Team BuildingCross-FunctionalStakeholder Alignment
Team Leadership
Cross-Functional Coordination
Event Planning
Mentorship

PCB Design

Stackup planning, impedance, pours, placement & routing, DRC, bring-up.

Altium Designer2–4 layerSI basics
Altium Designer
LTspice
Oscilloscope/LA
Linux
GitHub
Git

FPGA / RTL

Verilog/SystemVerilog, timing closure, verification, clean build flows.

QuartusModelSim100 MHz+
Quartus
ModelSim
SystemVerilog
Timing Closure
Testbench Dev
Git
Linux

Embedded Systems

STM32 (HAL), drivers, packets/CRC, USB-CDC, tooling & test harnesses.

C/C++UART/I²C/SPIPython
STM32
UART/I²C/SPI
USB-CDC
Linux
GitHub
C/C++
Python
Shell Scripting
Git

Mixed-Signal & Analog

Filters, sampling paths, power integrity awareness, measurement.

Scope/LADFMNoise
LTspice
Oscilloscope/LA
Linux

ASIC Design & Verification

Coverage-driven benches, hazards/forwarding, scripted regressions.

SVTcl/BashCI-like flows
SystemVerilog
ModelSim
Quartus
Timing Closure
Testbench Dev
Tcl/Bash
Python
Git

Extracurriculars

Strategy & Operations Lead

Global Spark
Global Spark
~2,000 applicants Role frameworks

Redesigned selection and role guides to scale reliably for a global hackathon.

Operations & Training Lead

UofT Engineering
UofT Engineering Leadership Training
550+ leaders Hybrid training

Built and delivered a cohesive program across live sessions and an online course.

Co-VP Competitions

Sustainable Engineers Association
SEA Case Competition
University-wide Judging rubrics

Launched a realistic case competition in power, climate, and logistics.

Student Mentor

CAGIS
CAGIS Workshop Mentoring
Hands-on STEM Renewables

Ran approachable workshops; partnered with Blue Sky Solar Racing on energy topics.

Contact

Download CV Email me LinkedIn
GitHub